North America

Verification & Semiconductor Futures USA - San Jose 2026

US chip verification and design conference, San Jose stop

Event Website Organiser Site

About this event

Verification & Semiconductor Futures USA runs technical tracks on formal verification, AI in DV, analogue/mixed-signal design and verification, and startups, at this San Jose stop.

Speakers

SS
Sean Safarpour
AMD
Customer
Keynote
BG
Bill Gascoyne
Blue Pearl Solutions
Vendor
CDC-RDC Verification Tutorial
DO
Dammy Olopade
Google
Customer
CDC-RDC Verification Tutorial
SC
Shankar Channabasappa
AVP Custom Silicon
Tessolve Semiconductor Inc
Vendor
Formal Verification and AI
NH
Nayab Hossain
CEO
Chipster
Customer
Formal Verification and AI
AK
Ankit Kumar Garg
Senior Manager, Formal Verification
Nvidia
Customer
Formal Verification and AI
AB
Andy Bond
Director RTL and Verification
OLIX
Customer
Using AI and Open Source in DV
GS
Gurpreet S Kalsi
Intel
Customer
Emerging Hardware Technologies
SS
Sasa Stamenkovic
Pure Silicon Solutions
Consultant
Using AI and Open Source in DV; Using AI in DV
FS
Frank Schirrmeister
Synopsys
Vendor
Emerging Hardware Technologies
SC
Suraj Chakravarthi Raja
MathWorks, Inc.
Vendor
Using AI and Open Source in DV
AN
Allen Nejah
SunMan Engineering, Inc.
Customer
Emerging Hardware Technologies
OG
Oscar Gustafsson
Linköping University
Academia
Using AI and Open Source in DV
AB
Abhyarthana Bisoyi
Odisha University of Technology and Research
Academia
Emerging Hardware Technologies
CS
Chiranjeevi Sirandas
Nvidia
Customer
Verifying Complex Systems
LK
Leon King
Cadence Design Systems
Vendor
AMS Design and Verification
SJ
Sivaharan Janahan
WRAXK Corp.
Customer
Verifying Complex Systems
KS
Krupa Shah
ASIC Engineering, Technical Leader
Cisco Systems, Inc.
Customer
Verifying Complex Systems
SS
Sandeep Sharma
Meta
Customer
AMS Design and Verification
DT
Dr. Tobias Ludwig
CEO
LUBIS EDA
Vendor
Formal Verification and AI
MB
Mike Bartley
SVP - VLSI Design
Alpinum Consulting
Consultant
Welcome Note
LK
Levon Khachatryan
Voskenai Ltd
Customer
AI Design IP
AM
Alexander Montgomerie-Corcoran
Heronic Technologies
Customer
AI Design IP
GC
Greg Chadwick
Fractile
Customer
AI Design IP
JL
James Lewis
RED Semiconductor International Ltd
Customer
AI Design IP
VP
Valentin Peltier
Secure-IC - A Cadence company
Vendor
Design
YE
Yassine Eben Aimine
Siemens EDA
Vendor
FPGA
LP
Lloyd Peto
NanoScope Services Ltd
Consultant
Design
GL
Gavin Lofts
Altera
Customer
FPGA
SG
Steinn Gustafsson
Chevin Technology
Consultant
FPGA
JD
John Darlington
Arm / University of Southampton
Customer
Design
RM
Rojalin Mishra
Riverlane
Customer
FPGA
FR
Francesco Raffaelli
KETS Quantum Security Ltd
Customer
Startups and Breakthrough Technologies
PR
Prof. Rob Young
Quantum Base
Academia
Startups and Breakthrough Technologies
SS
Simon Southwell
Wyvern Semiconductors
Customer
FPGA
PP
Phill Payne
Novomorphic
Customer
FPGA

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