North America

Verification & Semiconductor Futures USA - Austin 2026

US chip verification and design conference, Austin stop

Event Website Organiser Site

About this event

Verification & Semiconductor Futures USA runs technical tracks on formal verification, AI in DV, analogue/mixed-signal design and verification, and startups, at this Austin stop.

Speakers

ID
Irene Deng
NXP Semiconductors
Customer
Keynote
NN
Nandan Nayampally
Bayas Systems
Customer
Industry Keynote
DL
David Landoll
Product Manager, Questa Static & Formal Solutions
Siemens
Vendor
Formal Verification and AI
RL
Ranjit LoboPrabhu
Johns Hopkins University Applied Physics Laboratory
Academia
Emerging Hardware Technologies
PG
Paul Graykowski
Cadence
Vendor
Formal Verification and AI
JR
Jagadish Rongali
NXP Semiconductors Inc
Customer
Emerging Hardware Technologies
PK
Praveen Kumar Vagala
Independent Researcher
Consultant
Emerging Hardware Technologies
SS
Sunil Sahoo
Product Manager
Siemens EDA
Vendor
Using AI in VLSI & DV
SH
Shelly Henry
Moores Lab AI
Customer
Using AI in VLSI & DV
AK
Amit Kumar
Tenstorrent
Customer
Open Source EDA design tools
VK
Vikash Kumar
Senior Verification Architect
Arm
Customer
Using AI in VLSI & DV
A
Abinaya
NXP Semiconductors
Customer
Open Source EDA design tools
TH
Tom Henige
MathWorks, Inc.
Vendor
Using AI in VLSI & DV
MK
Madhukar Kadige
Beammwave AB
Customer
Open Source EDA design tools
DC
Daniel Cross
Solutions Architect
Cadence Design Systems
Vendor
AMS Design and Verification
VS
Vinoth Selvan
NVIDIA Corporation
Customer
Using AI in DV
EG
Efrain Gaxiola
Silicon Labs
Customer
AMS Design and Verification
SC
Shankar Channabasappa
AVP Custom Silicon
Tessolve Semiconductor Inc
Vendor
Formal Verification and AI
AB
Andy Bond
Director RTL and Verification
OLIX
Customer
Open Source EDA design tools
GS
Gurpreet S Kalsi
Intel
Customer
Emerging Hardware Technologies
SS
Sasa Stamenkovic
Pure Silicon Solutions
Consultant
Using AI in DV
FS
Frank Schirrmeister
Synopsys
Vendor
Using AI in DV
DT
Dr. Tobias Ludwig
CEO
LUBIS EDA
Vendor
Formal Verification and AI
MB
Mike Bartley
SVP - VLSI Design
Alpinum Consulting
Consultant
Welcome Note
LK
Levon Khachatryan
Voskenai Ltd
Customer
AI Design IP
AM
Alexander Montgomerie-Corcoran
Heronic Technologies
Customer
AI Design IP
GC
Greg Chadwick
Fractile
Customer
AI Design IP
JL
James Lewis
RED Semiconductor International Ltd
Customer
AI Design IP
VP
Valentin Peltier
Secure-IC - A Cadence company
Vendor
Design
YE
Yassine Eben Aimine
Siemens EDA
Vendor
FPGA
LP
Lloyd Peto
NanoScope Services Ltd
Consultant
Design
GL
Gavin Lofts
Altera
Customer
FPGA
SG
Steinn Gustafsson
Chevin Technology
Consultant
FPGA
JD
John Darlington
Arm / University of Southampton
Customer
Design
RM
Rojalin Mishra
Riverlane
Customer
FPGA
FR
Francesco Raffaelli
KETS Quantum Security Ltd
Customer
Startups and Breakthrough Technologies
PR
Prof. Rob Young
Quantum Base
Academia
Startups and Breakthrough Technologies
SS
Simon Southwell
Wyvern Semiconductors
Customer
FPGA
PP
Phill Payne
Novomorphic
Customer
FPGA

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