DVCon Europe
Design & verification conference (SystemVerilog/UVM, EDA verification ecosystem)
About this event
DVCon Europe brings the electronic design and verification community to Munich for two days. Organised by Accellera Systems Initiative, the 2026 programme covers SystemVerilog, UVM and the wider EDA verification ecosystem, with technical papers and tutorials aimed at chip design and verification engineers.
Who it's for
Genuinely useful for hardware and silicon design and verification professionals, RTL/SoC verification engineers, EDA tool vendors, IP providers, and standards-focused engineers. Not relevant for general software/IT, AEC/BIM, or enterprise asset-management audiences, content is deeply semiconductor/EDA-specific.
Social media & coverage
“Bipul Halder shares his DVCon India 2026 author badge for the conference happening September 1 to 3.”
“At DVCon US, session chair Kamel Belhous will lead a Regression Management Session showing live how AI is changing verification regressions.”
Official hashtags
Used by the organiser on X and LinkedIn. Follow along before, during and after the event.